The present invention relates to a method of optimizating logic synthesis, and more particularly to a method of logic synthesis using common and similar circuit extraction applicable to a large scale integrated circuit.
One of the conventional logic synthesis techniques is an operator sharing method wherein hardware descriptions at a resistor transfer level and operations not commonly executed are commonly held by switching with a multiplexer to reduce the number of the necessary arithmetic logic circuits.
Japanese laid-open patent publication No. 2-171862 discloses that common parts in the descriptions are extracted and defined as function macros and then transformed into a common reference form at a hierarchically low level so that an optimization process is executed only at the hierarchically low level to shorten the optimization processing time. Other cases are not commonly optimized even when a plurality of similar circuits exist.
In the above operator sharing system, arithmetic operations and hardware functions to be concurrently executed are not common subject matter. This means that it is impossible to shorten the optimization processing time.
The logic synthesis disclosed in the Japanese laid-open patent publication No. 2-171862 has an object to obtain simple and clear synthesis results in the circuit-divisional. method but is not intended to prevent deterioration of the optimization performance.
In the optimization processes, there are processes for which boundary conditions should be considered. The boundary conditions are largely different for every instance and optimal results might be not obtainable simply with reference to the hierarchically low level.
In the general logic synthesis other than the above, when a plurality of similar partial circuits exist in a large scale integrated circuit, various optimization processes are made to each partial circuit without common processing. This needs a long time for processing.
In the above circumstances, it had been required to develop a novel logic synthesis apparatus and method of logic synthesis wherein common and similar partial circuits are extracted from a large scale integrated circuit to shorten an optimization processing time without deterioration of optimization performance.